The present invention is directed to memory devices, and more particularly to methods and arrangements that provide improved control over certain memory device latencies associated with read and/or write operations.
Memory devices, such as, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), and the like, include at least one integrated circuit that is configured to store information in the form of binary data. In certain exemplary memory devices, at least one memory core is provided. The memory core has a plurality of memory cells operatively arranged as an array, such that the memory cells are associated with an addressable row and column. In this manner, data can be read from selected memory cells, and written to selected memory cells. Memory cells essentially act as capacitors that are charged/discharged as required to store an applicable binary value.
During a read operation, for example, an activate (row) command selectively causes the data in memory cells associated with a row to be loaded into a plurality of sense amplifiers (sense amps). Subsequently, a column (read) command is applied, which causes the data loaded into the sense amps to be asserted onto a data bus that can then be read by another circuit.
However, the sense amps require a certain amount of time to evaluate the memory cells following an activate (row) command. Thus, the application of the column (read) command needs to be timed or delayed accordingly. This delay is typically specified by a row-to-column delay (tRCD) in conventional DRAMs. There is also an inherent latency from the issuance of a read command until the corresponding data is available on the data bus.
To account for such delays/latency, a programmable column address strobe (CAS) latency can be enforced. For example, in certain conventional SDRAMs, this value is programmed as a CAS latency (CL) value in a mode register of the SDRAM. This programmability allows for latency minimization and yield enhancement.
The number of clocks cycles that must be allowed for the read to occur in a synchronous memory device system, is a function of the DRAM""s core response time, and the frequency of the clock signal being applied. In order to have minimal latency at any clock frequency, a register is often provided, to allow the number of clocks cycles between the read command and the data availability to be optimized. Additionally, not all memory devices will have the same minimum latency. Usually, in production, there will be a distribution of the minimum latency a DRAM core can achieve. By allowing the register to be programmed after the device has been tested, latency can be minimized over the yield distribution of the memory device.
These solutions introduce a dilemma during the memory device controller design phase. Here, a controller design must either optimize for pipeline efficiency under load, or unloaded latency when the pipeline is empty. Consequently, the CAS timing cannot be optimized to the applied workload. For example, the option of changing the register value to adjust for the applied workload will not work, since the task of writing to the register takes much longer than the read operation itself Moreover, the applied workload tends to change much more quickly than the register can.
Thus, there is a need for improved methods and arrangements that allow for the timing of commands and corresponding operations to better support the applied workload. Preferably, the improved methods and arrangements can be used to alter CAS timing to provide substantially minimal unloaded latency when needed and substantially optimal pipelined latency when needed.